|Year : 2012 | Volume
| Issue : 1 | Page : 41-44
Low-Power High-Speed Small Area Hybrid CMOS Full Adder
Amit Gupta1, RK Sharma1, Rasika Dhavse2
1 Department of Electronics and Communication Engineering, NIT Kurukshetra, Haryana, India
2 Department of Electronics and Communication Engineering, SVNIT Surat, India
|Date of Web Publication||24-Mar-2012|
Department of Electronics and Communication Engineering, NIT Kurukshetra, Haryana
Source of Support: None, Conflict of Interest: None
| Abstract|| |
A 20-transistor hybrid CMOS full adder circuit using small area transistors has been proposed. The circuit layout is designed with 0.18-μm n-well CMOS design rules. The post layout simulation has been carried out using TSMC018 technology file. The proposed adder circuit provides fully restored logic levels at the output for all input combinations up to an operating frequency of more than 500 MHz. The power dissipation, rise and fall times, and worst-case propagation delay as obtained from the proposed adder have been found to be better in comparison to other full adder circuits (which provide fully restored logic levels at the output) reported in the literature.
Keywords: Hybrid CMOS Full Adder, Driving capability, Fully restored logic levels, Low power
|How to cite this article:|
Gupta A, Sharma R K, Dhavse R. Low-Power High-Speed Small Area Hybrid CMOS Full Adder. J Eng Technol 2012;2:41-4
| 1. Introduction|| |
Full adders are used in large numbers in arithmetic processors. It is an important building block in multiplier circuits, dominantly influencing the speed of the latter. The desirable characteristics of a full adder circuit are low rise and fall times, small worst-case input to output delay, low power consumption, fully restored logic levels at the outputs for specified load, small silicon area required (i.e., low transistor count with small area transistors), and preferably equal input to output delay for all the outputs. This is particularly important when the full adder is used in Wallace tree implementation in a multiplier where a number of full adders need to be cascaded. Many full adder circuits have been proposed ,, . Due to very low static power consumption, CMOS have attracted most of the research effort. In general, these circuits have been divided into two categories: - the complementary CMOS (C-CMOS) and complementary pass transistor logic (CPL). The CPL implementation (also its variations such as transmission function and transmission gate) of full adder requires less number of transistors and therefore is area efficient but suffers from logic level degradation and poor driving capability. The C-CMOS design uses regular CMOS structure, is robust, provides fully restored logic levels at the output, has good driving capability, but requires larger number of transistors. A third category that utilizes both, the pass transistors and gates can be called hybrid CMOS  . Recently, a majority function full adder has also been proposed  and is claimed to be providing better performance at an operating frequency of 100 MHz. The other high performance adders are 28- transistor C-CMOS and 14-transistor adder circuit  . Many other , proposed adder circuits suffer from the problem of degradation of logic levels at the outputs and poor driving capability. A full adder circuit based on multi- threshold CMOS (MTCMOS) technology with improved delay characteristics has also been reported  .
In this article we introduce a 20- transistor full adder circuit using small/minimum area transistors. The performance of the proposed adder circuit is compared with 28 - transistor C-CMOS, 14- transistor hybrid CMOS, CPL, and MTCMOS full adders.
| 2. The Full Adder Circuit|| |
The Boolean equations describing the full adder are given below.
The sum output (S) may be generated with two cascaded XOR / XNOR gates. The carry output (C 0 ) can be generated by using two pass transistors to pass either input A or C in to the output terminal C0, depending on the value of (A ⊕ B).
The total power dissipation in a CMOS circuit is dominated by the dynamic power dissipation which is given by the equation
where 'f sw ', 'αi ', 'C i ' and 'V DD ' are maximum switching frequency, switching activity co-efficient at node 'i', capacitive load seen at node 'i' and supply voltage, respectively. It has been assumed that at each node the voltage swing is equal to supply voltage when the node changes its state. For a given switching frequency and supply voltage, the power dissipation can be reduced by reducing the node capacitances.
In the proposed full adder, the node capacitances have been minimized by use of minimum/small area transistors. The hybrid CMOS design style has been followed to achieve low transistor count and good driving cability.
The SUM (S) output has been generated using two XOR gates. The XOR function is obtained using a pass transistor-based XNOR gate followed by an inverter to restore the logic levels. For generating the carry output, transmission gates have been used instead of single pass transistors to pass inputs A or C. This resulted in improved logic levels at the output of the transmission gate leading to fully restored logic level at C 0 output. [Figure 1] shows the circuit diagram of proposed full adder.
In practical digital circuits, a functional block is driven through a gate / inverter and is required to drive a gate. The design of a digital circuit, therefore, should be tested with inputs applied through an inverter and another inverter / gate connected as load.
The circuit in [Figure 1] was tested with inputs applied through inverters and similar inverters connected as load. Both the input and load inverters are included in the circuit diagram. The optimum performance of the circuit in terms of speed, fully restored logic levels was obtained by choosing appropriate geometry of individual MOSFET. The pMOS and nMOS transistors used in the inverters have (W/L) ratio of (5/2) and (3/2), respectively. Inverters used in the full adder are also of same type. All transistors in XNOR gates have (W/L) of (6/2). The pMOS and nMOS transistors used in transmission gates have (W/L) of (6/2) and (3/2), respectively. The layout of the circuit in [Figure 1] (which includes the input inverters and load inverters) is shown in [Figure 2].
| 3. Simulation Results|| |
The layout shown in [Figure 2] was made using TSMC 0.18-μm process. The post layout simulation was done using Calibre and Eldo (Mentor Graphics Tools) with 1.8V power supply. The input and output voltage waveforms are given in [Figure 3]. The frequencies of input signals A, B and C were set to 500, 250 and 125 MHz respectively.
It can be seen that the output logic levels are fully restored and are free of glitches. The rise and fall times, propagation delay, and power dissipation as determined are given in [Table 1]. The power consumption was determined by multiplying the power supply voltage with average current drawn from the power supply.
The power consumption mentioned in the [Table 1] includes the power consumption in three input inverters and two load inverters which are external to 20-transistor full adder circuit. The response characteristics such as rise / fall times, propagation delay, and power dissipation were computed using EZwave tool.
| 4. Comparison with Other Full Adder Circuits|| |
A performance comparison of the proposed full adder with the other high performance full adders reported in the literature is given in [Table 2]. The performance parameters of other full adders have been quoted from reference  . It can be seen that the proposed adder offers considerably better performance in terms of both the speed and power consumption.
| 5. Conclusion|| |
A new 20-transistor full adder circuit has been proposed and implemented in 0.18μm technology. The proposed adder offers better performance than the other full adder circuits (implemented in same technology) reported in the literature. The proposed design is particularly suited for use in a binary multiplier circuit where a number of full adder circuits need to be cascaded. Any logic level degradation in such application would adversely affect the speed of the multiplier. Because of small area of transistors used and low transistor count, the proposed full adder would save silicon area for other circuits.
| References|| |
|1.||C. H. Chang, J. M. Gu, and M. Zhang, "A Review of 0.18 µm Full Adder Performances for Tree Structured Arithmetic Circuits", IEEE Trans. On VLSI Systems, Vol. 13, no. 6, pp. 686, 2005. |
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|3.||M. Vesterbacka, "A 14-Transistor CMOS Full Adder with Full Voltage Swing Nodes", Proc. IEEE Workshop on Signal Processing Systems, pp. 713, 1999. |
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| Authors|| |
Amit Gupta obtained his B.Tech (Electronics and Communication Engineering) from Kurukshetra University in the year 2004 and PG Diploma in VLSI Design in the year 2005. Presently he is working as a Lab Engineer at NIT Kurukshetra in the project Special Manpower Development Program in VLSI Design and also working for his M.Tech (Research) from Department of Electronics and Communication Engineering, SVNIT Surat. His major research interests are digital and analog IC design.
Dr. R. K. Sharma received the B.Sc.Engg degree in Electrical Engineering from Dayal bagh Educational Institute Agra in 1986, the M.Tech degree in Electronics and Communication engineering from Kurukshetra University Kurukshetra (through REC Kurukshetra) in 1992, and the Ph.D. degree in Electronics from Kurukshetra University Kurukshetra (through National Institute of Technology Kurukshetra) in 2007. He has been working at NIT Kurukshetra since 1989 and is currently holding a post of professor in Electronics and Communication engineering Department. Dr.R.K.Sharma has several research articles in international journals and conference proceedings.
Mrs. Rasika Dhavse has approximately 11 years of teaching experience in the area of electronics and Communication Engineering. She has been working as Assistant Professor at SVNIT Surat since July 2007. Her major research interests are nanotechnology, FGMOS, and VLSI Design. She has guided a number of M.Tech dissertations and has several research articles in international journals and conference proceedings.
[Figure 1], [Figure 2], [Figure 3]
[Table 1], [Table 2]