


ARTICLE 

Year : 2015  Volume
: 5
 Issue : 1  Page : 3640 

VLSI Design and Investigation of an Area Efficient and Low Power MODR2MDC FFT for MOMOOFDM
Kirubanandasarathy Nageswaran, Karthikeyan Kottaisamy
Department of Electronics and Communication Engineering, Syed Ammal Engineering College, Ramanathapuram, Tamil Nadu, India
Date of Web Publication  16Jan2015 
Correspondence Address: Kirubanandasarathy Nageswaran Department of Electronics and Communication Engineering, Syed Ammal Engineering College, Ramanathapuram, Tamil Nadu India
Source of Support: None, Conflict of Interest: None  Check 
DOI: 10.4103/09768580.149484
Abstract   
In this paper, an areaefficient low power fast Fourier transform processor is proposed for multi input multi outputorthogonal frequency division multiplexing (MIMOOFDM) in wireless communication system. It consists of a modified architecture of radix2 (R2) algorithm which is described as modified R2 multipath delay commutation (MODR2MDC). OFDM is a popular method for high data rate wireless transmission. This paper describes the very large scale integration design of an area efficient MODR2MDC FFT for MIMOOFDM system targeted to future wireless communication systems. The very high speed integrated hardware description language simulation results have been tested practically by implementing in the Altera development and education2 field programmed gate array (FPGA) development board. Also the existing OFDM system has been tested with these FFT algorithms and their performances were analyzed with respect to occupation of area in FPGA and power consumption. A lowpower and area efficient architecture enables the realtime operations of MIMOOFDM system. Keywords: Discrete Fourier transform, frequency division multiplexing, inverse fast Fourier transform, modifiedradix2 multipath delay commutation, multi input multi outputorthogonal frequency division multiplexing
How to cite this article: Nageswaran K, Kottaisamy K. VLSI Design and Investigation of an Area Efficient and Low Power MODR2MDC FFT for MOMOOFDM. J Eng Technol 2015;5:3640 
How to cite this URL: Nageswaran K, Kottaisamy K. VLSI Design and Investigation of an Area Efficient and Low Power MODR2MDC FFT for MOMOOFDM. J Eng Technol [serial online] 2015 [cited 2019 Apr 18];5:3640. Available from: http://www.onlinejet.net/text.asp?2015/5/1/36/149484 
1. Introduction   
Multi input multi outputorthogonal frequency division multiplexing (MIMOOFDM) is an efficient solution for transmitting and receiving the data over a long distance. The subcarrier frequency has been chosen in our proposed MIMOOFDM transceivers so that crosstalk between the subchannels are eliminated, hence, the intercarrier guard bands are not required ^{[1]} . This greatly simplifies the design of both the transmitter and the receiver; unlike conventional frequency division multiplexing, a separate filter for each subchannel is not required ^{[2]} . The orthogonally allows for the efficient modulator and demodulator implementation using the fast Fourier transform (FFT) algorithm ^{[3]} . OFDM transceiver is popular for wideband communications today by way of lowcost MIMOOFDM in wireless telecommunication system. It requires very accurate frequency synchronization between the receiver and they have reduced the complexity ^{[4]} . In the transmitter; with frequency deviation, the subcarriers shall no longer be orthogonal, causing intersymbol interference ^{[5]} . The 5/6 coding rate would be not effective for error correcting by a viterbi decoder ^{[6]} . This paper describes the very large scale integration (VLSI) implementation of the proposed modified radix2 multipath delay commutation (MODR2MDC) for MIMOOFDM systems, that is, MODR2MDC pipeline FFT based MIMOOFDM system. The R2 algorithm with multi delay commutation architecture is to support 4 channel 8, 16, 32, 64, 128, 512, 1024 and 2048 point FFT operations ^{[7],[ 8]} . We compare this proposed architecture with existing 8 point R2, R4 FFT and existing R2MDC FFT and also give the design and implementation results of the proposed MODR2MDC FFT processor.
2. Overview of MIMO OFDM   
The general transceiver structure of MIMOOFDM is presented in [Figure 1]. The system consists of N transmitter antennas and M receiver antennas. According to ^{[9]} and ^{[10]} , the cyclic prefix is assumed to be a longer than the channel delay spread. The OFDM signal for each antenna is obtained by using IFFT and can be detected by FFT. There are two methods widely used for transmitting MIMO data. If the channel has a negligible error rate, we can send several data simultaneously over multiple antennas. This is known as spatial multiplexing, which utilizes the spectrum very efficiently.  Figure 1: Multi input multi outputorthogonal frequency division multiplexing architecture
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In contrast, if the environment has high error rate, we transmit the same data over multiple antennas. This is called as spacetime coding. The purpose of this approach is to increase the diversity of MIMO to combat signal fading. The essential purpose of an MIMO system is to determine, which antenna is corresponding to which data on the receiver side. As shown in [Figure 1], R×1 receives data from all the transmitter antennas, T×1, T×2, T×3 and T×4. Thus, we must have a special decoding algorithm to identify which antenna has transmitted which data to R×1. N×M MIMOOFDM: N indicates the number of transmitter antennas and M indicates the number of receiver antennas, respectively. For example, 4×4 MIMOOFDM has four transmitter antennas and four receiver antennas as shown in [Figure 1].
OFDM is a multicarrier system where data bits are encoded to multiple subcarriers. Unlike single carrier systems, all the frequencies are sent simultaneously in time. OFDM offers several advantages over single carrier system like better multipath effect immunity, simpler channel equalization and relaxed timing acquisition constraints. However, it is more susceptible to local frequency offset and radio frontend nonlinearity ^{[11]} . The frequencies used in OFDM system are orthogonal. Neighboring frequencies with overlapping spectrum can, therefore, be used ^{[12]} .
3. Inverse Fast Fourier Transform/Fast Fourier Transform Algorithm   
In this section, a brief overview of IFFT and FFT algorithms is provided to be effectively used in OFDM applications. The Npoint Discrete FFT (DFT) is defined as:
X(k) is the k ^{th} harmonic and x(n) is the n ^{th} input sample. Direct DFT calculation requires a computational complexity of O (N ^{2} ). By using The CooleyTukey FFT algorithm, the complexity can be reduced to O (N log _{r} N). The CooleyTukey FFT is the most universal of all FFT algorithms, due to any factorization of N is possible.
The CooleyTukey algorithm is based on a divideconquers approach in the frequency domain and therefore is referred to as decimationinfrequency (DIF) FFT. The DFT formula is split into two summations:
X[k] can be decimated into evenand odd indexed frequency samples:
The computational procedure can be repeated through decimation of the N/2point DFTs X(2k) and DFTs X(2K+1). The entire algorithm involves log _{2} N stages, where each stage involves N/2 operation units (butterflies). The computation of the N point DFT via the DIF FFT, as in the decimationintime algorithm requires (N/2).log _{2} N complex multiplication and N.log _{2} N complex addition ^{[13]} .
4. Proposed Modified Radix2 Multipath Delay Commutation Architecture   
The R2 butterfly processor is consists of a complex adder and complex subtraction. Besides that, an additional complex multiplier for the twiddle factors W _{N} is implemented. The complex multiplication with the twiddle factor requires four real multiplications and two add/subtract operations as shown in [Figure 2].
The MODR2MDC is one of the commutated architectures of R2 FFT algorithm which is used to commutate the values as fast as possible in order to process the values and to commutate the FFT inputs, the architecture shown in the [Figure 3] is consists of different blocks which must be used in the MODR2MDC.  Figure 3: Proposed architecture block with modified radix2 multipath delay commutation fast Fourier transform
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One of the most straightforward approaches for pipeline implementation of R2 FFT algorithm is MODR2MDC architecture. It is the simplest way to rearrange data for the FFT/IFFT algorithm, the input data sequence are broken into two parallel data stream flowing forward, with correct distance between data elements entering the butterfly scheduled by proper delays ^{[14]} . At each stage of the 8point FFT in MODR2MDC architecture, half of the data flow is delayed via the memory (Register) and processed with the second half data stream ^{[15]} .
The A input comes from the previous component twiddle factor multipliers. The B output is fed to the next component, normally butterfly II (BF II). In first cycles, multiplexors direct the input data to the feedback registers until they are filled (position"0").
On next cycles, the multiplexers select the output of the adders or subtractors (position "1"), the butterfly computes a 2point DFT with incoming data and the data stored in the feedback registers. The architecture of BF I and BF II supporting two receive chains is shown in [Figure 4] (a) and 4 (b). In BF I structure, the sample routing multiplexers and demultiplexers at the input and output of the BFrandom access memories (BFRAMs) are controlled based on c2 and c3 control signals while the computation unit is controlled by c1 control signal. Depending on the programming of number of receive chains, the extra BFRAMs are enabled. Based on the requirement extra buffers can be extended to the existing BF structure. Since the handling −1, +j and −j multiplication is handled inside the BF II structure, two control signals c1 and c2 are used in the basic computation unit. The multiplexers and the demultiplexers are controlled by c3 and c4 control signals. The product with '−j' term is implemented by swapping the real and imaginary part considering the sign of the sample. The algorithm used here is to commutate the R2 algorithm in the IFFT architecture ^{[2]} . In order to optimize the processor, the proposed shift and add method that eliminates the nontrivial complex multiplication with the twiddle factors (W8 ^{1} , W8 ^{3} ) and implements the processor without complex multiplication. The proposed butterfly processor performs the multiplication with the trivial factor W8 ^{2} = −j by switching from real to imaginary part and imaginary to real part, with the factor W8 ^{0} by a simple cable. With the nontrivial factors W8 ^{1} = e^{−jπ/4}, W8 ^{3} = e^{−j3π/4}, the processor realize the multiplication by the factor 1/√2 using hardwired shift/add operation as shown in [Figure 5].  Figure 4: (a) Basic butterfly (BF) I structure and (b) Basic BF II structure
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5. Results and Discussion   
The prime objective is to construct a FFT in order to have low power consumption and lesser area. The parameters (i) power consumption (ii) area occupancy were given due consideration for comparing the proposed circuit with other FFTs. The experimental results analysis consists of six different types of architectures such as R2, R4, spilt radix, mixed R4/2, R2MDC and MOD R2MDC FFT that can be implemented in the Altera cyclone II development and education 2 (DE2) field programmed gate array (FPGA). We have designed all coding using hardware description language. To get power, and area report, we use XILINX ISE design suite 10.1 as synthesis tool and modelsim 6.3c for simulation. The purpose is to determine the resource usage of this proposed design attempts to eliminate the complex multiplication, hence avoid this expensive operation of multiplication and consumes less chip area. The proposed MODR2MDC FFT gives better result than R2 FFT and existing R2MDC FFT in terms of area and power consumption as shown in the [Table 1].  Table 1: Comparison results of proposed modr2mdc FFT with existing r2 mdc and radix2 architecture
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The simulation results for various FFT algorithms have been tested practically by implementing in the Altera DE2 FPGA development board. The QuartusII tool is used to download the design in to FPGA development board. In the FPGA board, the reset signal input is connected to the rightmost switch. For set the binary inputs at the remaining switches, after the process in the FPGA, the outputs are seen in light emitting diode display in the board. Also these FPGA output can be verified with simulation results obtained using Modelsim 6.3c. The FPGA board has developed to verify their circuit behavior and implementation of MIMOOFDM in wireless telecommunication system.
6. Conclusion   
In this work, several FFT algorithms such as R2, R2MDC and the proposed MOD R2MDC FFT were designed using VLSI design process and their performances were analyzed. From the results, it was observed that the proposed MOD R2MDC uses least numbers of configurable logic block slices and save the area of approximately 10% and it consumes <20% of power when compared to other FFT. It is seen that the new MODR2MDC FFT algorithm provides lesser area and low power consumption. The very high speed integrated hardware description language simulation results have been tested practically by implementing in the Altera DE2 FPGA development board. Also the existing OFDM system has been tested with these FFT algorithms and their performance was analyzed with respect to occupation of area in FPGA and power consumption. We conclude that the proposed MODR2MDC architecture is occupied a low area and consumed less power than the existing R2 and R2MDC FFT algorithm architecture. The proposed architecture is shows that it can be used in for low power applications such as MIMOOFDM in wireless communication system.
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Authors   
Dr. Kirubanandasarathy , N received a first class B.Eng. degree in Electrical and Electronics Engineering from Madurai Kamaraj University, Tamilnadu, India, in 2002 and a first class M.Eng. Degree in Applied Electronics from Anna University, Tamilnadu, India in 2004, and Ph.D. from St.Peter's institute of Higher Education and Research, Tamilnadu, India in 2013. Currently, he is working as a Professor in the department of Electronics and communication engineering of Syed Ammal Engineering College, Ramanathapuram, Tamilnadu, India. His fields of interest include low power VLSI design and Communication system.
Dr. Karthikeyan , K received a first class with distinction B.Eng. degree in Electrical and Electronics Engineering from Madurai Kamaraj University, India, in 2002, and a first class with distinction M.Eng. degree in Power systems from Anna University, India, in 2004, and the Ph.D. degree from Indian Institute of Technology Madras, India, in 2008. Currently, he is working as a Professor in the Department of Electronics and Communication Engineering of Syed Ammal Engineering College, Ramanathapuram, Tamilnadu, India. His fields of interest include VLSI system design and Power electronics applications in Power system.
[Figure 1], [Figure 2], [Figure 3], [Figure 4], [Figure 5]
[Table 1]
