Journal of Engineering and Technology

ARTICLE
Year
: 2012  |  Volume : 2  |  Issue : 1  |  Page : 41--44

Low-Power High-Speed Small Area Hybrid CMOS Full Adder


Amit Gupta1, RK Sharma1, Rasika Dhavse2 
1 Department of Electronics and Communication Engineering, NIT Kurukshetra, Haryana, India
2 Department of Electronics and Communication Engineering, SVNIT Surat, India

Correspondence Address:
Amit Gupta
Department of Electronics and Communication Engineering, NIT Kurukshetra, Haryana
India

A 20-transistor hybrid CMOS full adder circuit using small area transistors has been proposed. The circuit layout is designed with 0.18-μm n-well CMOS design rules. The post layout simulation has been carried out using TSMC018 technology file. The proposed adder circuit provides fully restored logic levels at the output for all input combinations up to an operating frequency of more than 500 MHz. The power dissipation, rise and fall times, and worst-case propagation delay as obtained from the proposed adder have been found to be better in comparison to other full adder circuits (which provide fully restored logic levels at the output) reported in the literature.


How to cite this article:
Gupta A, Sharma R K, Dhavse R. Low-Power High-Speed Small Area Hybrid CMOS Full Adder.J Eng Technol 2012;2:41-44


How to cite this URL:
Gupta A, Sharma R K, Dhavse R. Low-Power High-Speed Small Area Hybrid CMOS Full Adder. J Eng Technol [serial online] 2012 [cited 2020 Aug 6 ];2:41-44
Available from: http://www.onlinejet.net/article.asp?issn=0976-8580;year=2012;volume=2;issue=1;spage=41;epage=44;aulast=Gupta;type=0